A 16 kb ferroelectric nonvolatile memory with a bit parallel architecture
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 242-243,
- https://doi.org/10.1109/isscc.1989.48273
Abstract
The authors describe an experimental 16-kb nonvolatile memory using two memory cells per bit with one transistor and one ferroelectric capacitor per memory cell. The RAM measures 5 mm*7 mm with 462 mu m/sup 2/ per bit. It is built in a 2- mu m CMOS n-well process and has a chip-enable access time of 200 ns. The authors also demonstrate a bit-parallel architecture in which the common plate of the capacitors runs parallel to the bit lines and connects all bits in a given column. The typical characteristics of the device are given.Keywords
This publication has 2 references indexed in Scilit:
- An experimental 512-bit nonvolatile memory with ferroelectric storage cellIEEE Journal of Solid-State Circuits, 1988
- A non-volatile memory cell based on ferroelectric storage capacitorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987