Substrate effects on performance of InP MOSFETs

13 May 1982

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 18 (10) , 415-417
https://doi.org/10.1049/el:19820285

Abstract

InP MOSFET devices with a SiO₂ dielectric layer have been fabricated on p-type and SI substrates. Surface mobilities in the range 250 to 750 cm² V⁻¹ s⁻¹ have been routinely obtained from all substrates except those from one crystal of Fe-doped SI InP. Defect etching studies have revealed large prismatic dislocation loops in this crystal. A correlation between these observations is proposed.

Keywords

SIO2 DIELECTRIC LAYER
DEFECT ETCHING
SURFACE MOBILITIES
SUBSTRATE EFFECTS
INP MOSFETS
III-V SEMICONDUCTORS
PRISMATIC DISLOCATION LOOPS

This publication has 1 reference indexed in Scilit:

MISFET and MIS Diode Behaviour of Some Insulator-InP Systems
Published by Springer Nature ,1981