Buffer memory requirements in DSP applications
- 17 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 7 references indexed in Scilit:
- GRAPE-II: a tool for the rapid prototyping of multi-rate asynchronous DSP applications on heterogeneous multiprocessorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Geometric parallelism and cyclo-static data flow in GRAPE-IIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Scheduling dynamic dataflow graphs with bounded memory using the token flow modelPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- Rapid prototyping for DSP systems with multiprocessorsIEEE Design & Test of Computers, 1991
- Consistency in dataflow graphsIEEE Transactions on Parallel and Distributed Systems, 1991
- Synchronous data flowProceedings of the IEEE, 1987
- Static Scheduling of Synchronous Data Flow Programs for Digital Signal ProcessingIEEE Transactions on Computers, 1987