Improved planarization techniques applied to a low dielectric constant polyimide used in multilevel metal ICs

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Abstract
A low dielectric constant fluorinated polyimide has been employed as the interlevel dielectric in a four-level metal VLSI process. Due to the stringent requirement of a near global planar topography compared with the partial planarizing properties of the polyimide, two advanced approaches were evaluated: (1) a "negative-image" sacrificial photoresist etchback process, and (2) a photoresist image reversal plus dry etch process. Both techniques remove the polyimide from the surface of the metal while leaving polyimide "islands" or "plugs" between the metal features. A second polyimide layer is then applied. The planarity of the finished structure is controlled by the thickness of the initial polyimide layer, the plasma etch process, and the planarizing characteristics of the second or "recoat" polyimide film. The improved global planarity achievable using the advanced techniques were compared to a standard single spin polyimide process using surface profilometer profiles and cross-sectional SEM micrographs. The pros and cons of the two planarization techniques are also discussed.

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