A 64Kb CMOS RAM

1 January 1982

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXV, 258-259
https://doi.org/10.1109/isscc.1982.1156311

Abstract

This report will cover the design of a fault-tolerant 8K×8b static RAM using a double polysilicon CMOS technology. Memory access is 70ns typically, while consuming 15mW operating power and 10μW standby power.

Keywords

READ-WRITE MEMORY
RANDOM ACCESS MEMORY
LATCHES
SEMICONDUCTOR DEVICE MEASUREMENT
DECODING
CMOS PROCESS
MOS DEVICES
DRIVER CIRCUITS
DELAY LINES
FABRICATION

This publication has 3 references indexed in Scilit:

2K×8b HCMOS static RAMs
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1980
A 64Kb static RAM
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1980
Fully static 16Kb bulk CMOS RAM
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1980