An algorithm for the partitioning of logic circuits
- 1 January 1984
- journal article
- Published by Institution of Engineering and Technology (IET) in IEE Proceedings E Computers and Digital Techniques
- Vol. 131 (4) , 113-118
- https://doi.org/10.1049/ip-e.1984.0021
Abstract
The exhaustive testing of today's digital circuits is not possible, owing to the vast test sequences which would have to be applied. Breaking down the circuit into manageable subcircuits (partitioning) makes exhaustive testing practicable. Partitioning has previously been done by the designer of the circuit in rather an ad hoc manner. The paper describes an algorithm which can be used to find the partitioning points in a circuit. The algorithm is illustrated for circuits containing reconvergent and nonreconvergent fan-outs.Keywords
This publication has 1 reference indexed in Scilit:
- Test generation costs analysis and projectionsPublished by Association for Computing Machinery (ACM) ,1980