1.5-V low supply voltage 43-Gb/s delayed flip-flop circuit

1 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 10647775,p. 169-172
https://doi.org/10.1109/gaas.2003.1252387

Abstract

This paper reports the first low (1.5 V) supply voltage D-F/F able to run at a full rate of over 43 Gb/s. The proposed F/F circuitry incorporates parallel current switching together with inductive peaking, a combination that makes it suitable for over-43-Gb/s operation at a supply voltage as low as 1.5 V. The D-F/F, implemented through an InP-HBT process, provided 43 Gb/s error free operation with a large clock phase margin of 232 degrees. Moreover, the D-F/F produced a well-opened 50 Gb/s eye diagram. Power dissipation (P/sub diss/) of the D-F/F core circuit was reduced to 40 mW, which is less than one-tenth that of our conventional D-F/F. The F/F circuitry should help enable development of a low-P/sub diss/ 43 Gb/s full-rate module with a 1.5 V range supply voltage, which can be seamlessly connected with high-speed CMOS I/O circuits.

Keywords

This publication has 2 references indexed in Scilit:

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Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
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