A real time FFT chip set: architectural issues

4 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 385-388 vol. 2
https://doi.org/10.1109/icpr.1990.119387

Abstract

The tradeoffs involved in the design of a real-time 40-MHz fast Fourier transform (FFT) chip set are discussed. Tradeoffs involving the algorithmic organization, device partitioning, the data format, and device architecture are examined. The chip set can compute FFTs with up to 2048 points at 40-MHz data rates (or 80-MHz data rates for real data) by using up to 20 chips or at 3-MHz rates when using only three devices. The 1.5- mu CMOS chip set has been designed, fabricated, and tested and is fully functional.

Keywords

SHIFT REGISTERS
READ ONLY MEMORY
LOGIC DEVICES
COMPUTER ARCHITECTURE
COST FUNCTION
LARGE SCALE INTEGRATION
DIGITAL SIGNAL PROCESSING CHIPS
PARTITIONING ALGORITHMS
FLEXIBLE PRINTED CIRCUITS
TESTING

This publication has 0 references indexed in Scilit: