An analytical quasi-saturation model for vertical DMOS power transistors
- 1 March 1993
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 40 (3) , 676-679
- https://doi.org/10.1109/16.199343
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- Analysis of the quasi-saturation behavior considering the drain-to-source voltage and cell-spacing effects for a vertical DMOS power transistorSolid-State Electronics, 1993
- A circuit simulation model for high-frequency power MOSFETsIEEE Transactions on Power Electronics, 1991
- Optimally scaled low-voltage vertical power MOSFETs for high-frequency power conversionIEEE Transactions on Electron Devices, 1990
- Physical DMOST modeling for high-voltage IC CADIEEE Transactions on Electron Devices, 1990
- Study of the quasi-saturation effect in VDMOS transistorsIEEE Transactions on Electron Devices, 1986
- Carrier mobilities in silicon empirically related to doping and fieldProceedings of the IEEE, 1967