Systolic array processor for MVDR beamforming
- 1 January 1989
- journal article
- Published by Institution of Engineering and Technology (IET) in IEE Proceedings F Radar and Signal Processing
- Vol. 136 (2) , 75-80
- https://doi.org/10.1049/ip-f-2.1989.0013
Abstract
An efficient systolic array for computing the minimum variance distortionless response (MVDR) from an adaptive antenna array is described. It is fully pipelined and based on a numerically stable algorithm which requires O(p2 + Kp) arithmetic operations per sample time, where p is the number of antenna elements and K is the number of look direction constraints.Keywords
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