Hierarchical Design Verification for Large Digital Systems
- 1 January 1981
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 105-112
- https://doi.org/10.1109/dac.1981.1585339
Abstract
This paper describes a hierarchical design verification system, consisting of a logic verification subsystem, MIXS (1), a timing verification sybsystem, NELTAS(2), and a hierarchical data base. MIXS is a mixed level simulator, which can handle both functional and chip or gate level models with a unified simulation mechanism based on “node” model concept. NELTAS analizes delay time by tracing logical paths and calculating their media delay time. Both subsystems have hierarchical processing capability.Keywords
This publication has 1 reference indexed in Scilit:
- Design Verification and Performance AnalysisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1978