Radiation hardening of CMOS/SOS integrated circuits

1 December 1974

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science

Vol. 21 (6) , 152-158
https://doi.org/10.1109/TNS.1974.6498921

Abstract

Radiation tolerant CMOS circuits can be made by building them in a thin film of silicon-on-sapphire (SOS) with a hard gate dielectric. Radiation effects in MOS devices are reviewed, and the problems associated with radiation tolerant CMOS/SOS devices are described. Some gate dielectric techniques which show promise in hardening CMOS circuits are presented, and the radiation behavior of Al2O3 gate dielectrics are described.

Keywords

TOLERANT
BUILDING
BEHAVIOR
HARDENING
CMOS CIRCUITS
CMOS/SOS
PROMISE