Adaptive Wafer Scale Integration
- 1 January 1980
- journal article
- Published by IOP Publishing in Japanese Journal of Applied Physics
- Vol. 19 (S1)
- https://doi.org/10.7567/jjaps.19s1.193
Abstract
Based on an in-situ electrical alterable nonvolatile semiconductor memory, the MNOS transistor, an adaptive interconnect is developed to implement wafer-scale integration. Experimental validation of the interconnect is reported. The interconnect concept is further extended to the design of semiconductor mass memory and the design of an adaptive voter to implement fault tolerant systems.Keywords
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