Architecture for VLSI Design of Reed-Solomon Decoders
- 1 February 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-33 (2) , 178-189
- https://doi.org/10.1109/TC.1984.1676409
Abstract
In this paper, the known decoding procedures for Reed-Solomon (RS) codes are modified to obtain a repetitive and recursive decoding technique which is suitable for VLSI implementation and pipelining. The chip architectures of two basic building blocks for VLSI RS decoder systems are then presented. It is shown that a VLSI RS decoder has the potential advantage of achieving a high decoding speed through parallel-pipeline processing.Keywords
This publication has 9 references indexed in Scilit:
- Bit-serial Reed - Solomon encodersIEEE Transactions on Information Theory, 1982
- Architecture for VLSI Design of Reed-Solomon EncodersIEEE Transactions on Computers, 1982
- The technology of error-correcting codesProceedings of the IEEE, 1980
- A Cellular-Array Multiplier for GF(2m)IEEE Transactions on Computers, 1971
- On decoding of Reed-Solomon codesIEEE Transactions on Information Theory, 1971
- The Fast Fourier Transform in a Finite FieldMathematics of Computation, 1971
- Shift-register synthesis and BCH decodingIEEE Transactions on Information Theory, 1969
- Cyclic decoding procedures for Bose- Chaudhuri-Hocquenghem codesIEEE Transactions on Information Theory, 1964
- Computation with finite fieldsInformation and Control, 1963