The K2 parallel processor: architecture and hardware implementation

4 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 92-101
https://doi.org/10.1109/isca.1990.134512

Abstract

K2 is a distributed-memory parallel processor designed to support a multiuser, multitasking, time-sharing operating system and an automatically parallelizing Fortran compiler. The architecture and the hardware implementation of K2 are presented. The authors focus on the architectural features required by the operating system and the compiler. A prototype machine with 24 processors is currently being developed.

Keywords

This publication has 18 references indexed in Scilit:

Three-dimensional simulation of complex semiconductor device structures
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
iWarp: an integrated solution to high-speed parallel computing
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
A program debugger for a systolic array: design and implementation
Published by Association for Computing Machinery (ACM) ,1988
Efficient mapping and implementation of matrix algorithms on a hypercube
The Journal of Supercomputing, 1988
Locality, Communication, and Interconnect Length in Multicomputers
SIAM Journal on Computing, 1988
Nearest-Neighbor Mapping of Finite Element Graphs onto Processor Meshes
IEEE Transactions on Computers, 1987
The Warp Computer: Architecture, Implementation, and Performance
IEEE Transactions on Computers, 1987
Communication efficient basic linear algebra computations on hypercube architectures
Journal of Parallel and Distributed Computing, 1987
A Microprocessor-based Hypercube Supercomputer
IEEE Micro, 1986
Memory requirements for balanced computer architectures
ACM SIGARCH Computer Architecture News, 1986