Standby voltage scaling for reduced power

1 March 2004

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 639-642
https://doi.org/10.1109/cicc.2003.1249477

Abstract

Lowering V/sub DD/ during standby mode reduces power by decreasing both voltage and current. Measurements of a 0.13 /spl mu/m test chip show that reducing V/sub DD/ to near the point where state is lost gives the best power savings. We propose closed-loop voltage scaling that uses "canary" flip-flops for achieving these savings. This approach provides over 2/spl times/ higher savings than optimal open-loop approaches without loss of state.

Keywords

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