MISC

Publisher Website
Google Scholar
Abstract
This paper describes a single chip Multiple Instruction Stream Computer (MIX) capable of extracting instruction level p&llelism from a broad spectrum of programs. The MISC architecture uses multiple asynchronous processing elements to separate a program into streams that can be executed in parallel, and integrates a conff ict-free message passing system into the lowest level of the processor design to facilitate low latency intraMISC communication. This approach allows for increased machine parallelism with minimal code expansion, and provides an alternative approach to single instruction stream multi-issue machines such as SuperScalar and VLIW. 1. The MISC Design The MISC processor, a direct descendant of the PIPE project [CGKP87,GHLP85] will exploit both the instruction and data parallelism available in a task by combining the capabilities of traditional data parallel architectures with those found in machines &signed to exploit instruction level parallelism. Unlike the two processor PIPE design, the MISC system is capable of balancing the processor load of instructions performing memory access and execute operations among four processors. The characteristics of the MISC design also allow the introduction of a number of new and unique instructions, like the Sentinel and Vector instructions described later in this paper. As its name indicates, MISC is composed of multiple Processing Elements (PEs) which cooperate in the execution of a task. MISC is technically a message passing system where data can be sent between processors as easily as it can be transferred between processor registers. The MISC system consists of four Processing Elements (PEs), a dual bank-selected data cache @Cache) and a set of internal data paths used to transmit data among PEs and the DCache. The component design of MISC is illustrated in Figure 1. Each PE executes asynchronously from other PEs and the DCache. The internal datapaths are used to facilitate communication between elements (PEs and/or DCache). Each data path is controlled by a single element; for instance, the internal data path labeled PBUS 1 is controlled (written) solely by PEl. Each PE has its own such bus (PBUS (la)), and the data cache controls two busses (CBUS 1 and CBUS2). In addition to 32 data lines, each internal bus also consists of routing lines and busy lines. The routing lines are used to identify the destination of a given message; a routing line exists for each possible destination (PE( l-41 and D&he). Collectively, the routing lines specify I which subset of destinations should receive a message. In order to broadcast a message to all other processors, a Processing Element would therefore assert the roufing line for each destination, enabling up to 5 data transfers in a single PBUS or CBUS operation. The busy lines are asserted by each potential destination to indicate it’s inability to accept more data at the present time. When a processor wants to send a message, it determines the desired roufe and compares this with the busy lines associated with it’s own bus. If all elements of the destination route are capable of receiving the data, then the data and routing information is placed onto the bus. Transmission of data does not require the communicating PEs to synchronize at the transfer of the message; instead, data buffers (queues) are provided to store messages that have been sent but not yet processed by the destination. Two separate bank selected I/O channels support the transmission of data between the MISC chip and the rest of the system (main memory). These channels are controlled by the DCache. 1.1. Processing Element Structure

This publication has 2 references indexed in Scilit: