Flag-algebra: a new concept for the realisation of fully parallel associative architectures

Abstract
The paper describes a new concept for the design of parallel-working associative memory and processor architectures, which is able to process arithmetical operations as well as complex search-operations for the sets of data in parallel. The proposed concept is based on a transformation method. It maps a set of word-oriented data into flag-oriented data. Each word of the set is represented each by a flag in a flagvector. The position of a flag in the flagvector is defined by the transformation and corresponds to the value of the transformed word. To obtain parallelism for various operations, the flags of the flagvector will be processed simultaneously. The result of these operations will also be flags. They can be retransformed to word-oriented data. A new algebra called flag-algebra to investigate operations on the flagvector will be introduced. This algebra is the isomorph to the set-theory and Boolean algebra. The most important axioms and laws of calculation in this algebra will be described. They can be seen as a substantial basis for the development of flag-oriented hardware systems. Based on this algebra, the architecture of an associative monoprocessor will be presented to process arithmetical as well as complex search operations in parallel. Furthermore, some languages adequate for this architecture and the performance of the processor will be discussed.

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