Nonlinear compensation for finite word length effects of an LMS echo canceller algorithm suitable for VLSI implementation
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 15206149,p. 1487-1490
- https://doi.org/10.1109/icassp.1988.196884
Abstract
When an algorithm for echo cancellation is to be implemented in VLSI, it is essential to minimize the word length of the coefficients for economical reasons. While insufficient word length significantly degrades the performance of the canceller, it is possible to compensate for its effects by using a nonuniform number representation system, i.e. pseudo-floating-point arithmetic. Such an algorithm, using 10 bits, is discussed and its performance is compared with that of ordinary fixed-point algorithms with various number of bits. A multichannel echo-canceller chip has been built using this algorithm. It is used successfully in a T1 echo canceller system.Keywords
This publication has 2 references indexed in Scilit:
- Echo cancellation algorithmsIEEE ASSP Magazine, 1984
- A Single-Chip VLSI Echo CancelerBell System Technical Journal, 1980