Low-temperature CMOS 8 × 8 bit multipliers with sub-10-ns speeds

1 January 1987

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 34 (1) , 94-100
https://doi.org/10.1109/T-ED.1987.22890

Abstract

Low-temperature (77, 4.2 K) operation is proposed for bulk CMOS devices for use in super-fast VLSI applications. Symmetrical variations of both types of MOSFET parameters with respect to temperature and latchup immunity make CMOS a very promising device technology at low temperatures. To demonstrate the performance advantage of circuit operation at low temperatures, multipliers with two different circuit configurations are designed and fabricated with a gate length of 1.3 µm. Multiplication speeds of 8.0 and 6.6 ns are obtained with CMOS circuit configurations at 4.2 K and with pulsed-p-load/CMOS circuit configurations at 77 K, respectively.

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