FPGA-based high performance page layout segmentation
- 23 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A page layout segmentation algorithm for locating text, background and halftone areas is presented. The algorithm has been implemented on Splash 2-an FPGA-based array processor. The speed as determined by the Xilinx synthesis tools projects an application speed of 5 MHz. For documents of size 1,024/spl times/1,024 pixels, a significant speedup of two orders of magnitude compared to a SparcStation 20 has been achieved.Keywords
This publication has 9 references indexed in Scilit:
- Image segmentation techniquesPublished by Elsevier ,2006
- Convolution on Splash 2Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Page segmentation using texture discrimination masksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Learning texture discrimination masksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1996
- Address Block Location Using Color and Texture AnalysisCVGIP: Image Understanding, 1994
- Document image understanding: geometric and logical layoutPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1994
- A review on image segmentation techniquesPattern Recognition, 1993
- Page segmentation and classificationCVGIP: Graphical Models and Image Processing, 1992
- Text segmentation using gabor filters for automatic document processingMachine Vision and Applications, 1992