Error tolerance in parallel simulated annealing techniques
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
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- Parallel algorithms for chip placement by simulated annealingIBM Journal of Research and Development, 1987
- Global Wiring by Simulated AnnealingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983
- Optimization by Simulated AnnealingScience, 1983