Automating Technology Relative Logic Synthesis and Module Selection
- 1 April 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 2 (2) , 94-105
- https://doi.org/10.1109/tcad.1983.1270025
Abstract
This paper discusses a design aid which translates the data part of a functional level digital design into a logic level design through the specification of module set information. The constraint driven automatic methodology is discussed and results of using the design aid are presented. Predictors are developed to estimate the logic level design space, thus providing early feedback within the design process.Keywords
This publication has 3 references indexed in Scilit:
- A design methodology and computer aids for digital VLSI systemsIEEE Transactions on Circuits and Systems, 1981
- Instruction set processor specifications (ISPS): The notation and its applicationsIEEE Transactions on Computers, 1981
- Register-Transfer Level Digital Design Automation: The Allocation ProcessPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1978