GByte-class skewless parallel-optical-data-link subsystem

24 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 2, 63-64 vol.2
https://doi.org/10.1109/leos.1996.571550

Abstract

This paper describes 48 x 100 Mbit/s data link subsystem using a 6 x 1.1 Gbit/s arrayed optical transceiver module and 15-ns deskew function ICs. This link will be applied to the real world computing (RWC)-1, which is one of the massively parallel computer with 1,000-class processor elements.

Keywords

OPTICAL ARRAYS
OPTICAL TRANSMITTERS
CONCURRENT COMPUTING
OPTICAL RECEIVERS
CLOCKS
OPTICAL INTERCONNECTIONS
BIT ERROR RATE
MASTER-SLAVE
LABORATORIES
NATIONAL ELECTRIC CODE

This publication has 1 reference indexed in Scilit:

Super-threading
Published by Association for Computing Machinery (ACM) ,1993