A 0.9 V 150 MHz 10 mW 4 mm/sup 2/ 2-D discrete cosine transform core processor with variable-threshold-voltage scheme

23 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01936530,p. 166-167,
https://doi.org/10.1109/isscc.1996.488555

Abstract

This two-dimensional 8/spl times/8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV-resolution in a 0.3 /spl mu/m CMOS triple-well double-metal technology operates at 150 MHz from a 0.9 V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3 V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed, standby power and chip area.

Keywords

This publication has 2 references indexed in Scilit:

200 MHz video compression macrocells using low-swing differential logic
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
Self-adjusting threshold-voltage scheme (SATS) for low-voltage high-speed operation
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002