SOI-CMOS technology with monolithically integrated active and passive RF devices on high resistivity SIMOX substrates

1 January 1996

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 130-131
https://doi.org/10.1109/soi.1996.552528

Abstract

Summary form only given. A Silicon-On-Insulator (SOI) CMOS technology has been developed for microwave applications up to 5 GHz. The technology is based on a manufacturable, near-fully-depleted 0.8 /spl mu/m CMOS-VLSI technology with very high resistivity SIMOX substrate, typically >10 k/spl Omega/cm. The thicknesses of gate oxide, silicon film and buried oxide are 10 nm, 100 nm and 400 nm, respectively. A TiSi/sub 2/ self-aligned silicide formation is used to lower the resistance of the gate and source/drain regions. The process is completed with a two-level AlSi metallization featuring TiN-barrier, tungsten plug and stacked contacts and vias. Barrier, tungsten plug and metallization reinforce the polycide gates for the RF transistors to further reduce the gate resistance. The two-level metallization is used for the fabrication of metal1-metal2 capacitors with SiO/sub 2/ interlayer dielectric, planar RF inductors and metal coplanar waveguides. The RF SOI-CMOS process steps are similar to typical submicron CMOS processing steps except that well and field implants are eliminated in the SOI-CMOS technology.

Keywords

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