Effects of Process‐Induced Damage on Metal Oxide Semiconductor Structures with 115 Å Thin Gate Oxides

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Abstract
After thermal oxidation, the oxidized silicon substrates were exposed to Si ion beams. Metallization was then carried out to complete the metal oxide semiconductor (MOS) structures. Comprehensive small signal admittance measurements were made. The admittance data were analyzed by the standard approach used for the silicon/silicon dioxide interface states. The results for ion‐beam‐exposed samples exhibited many anomalies. In these samples, the trap density obtained from the ac conductance was much smaller than that obtained from the static capacitance. Second, very high and very low state capture cross sections were obtained. Third, vs. ω profiles exhibited multiple peaks. These and other anomalies appear to be caused by the generation of a high density of defects in the bulk silicon and the oxide and the formation of a high resistivity layer in the silicon subsurface. These results underscore the need for a different circuit model to analyze the admittance data of process‐damaged MOS structures.

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