A 0.13 μm CMOS platform with Cu/low-k interconnects for system on chip applications

13 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 101-102
https://doi.org/10.1109/vlsit.2001.934969

Abstract

We describe an advanced 0.13 /spl mu/m CMOS technology platform optimized for density, performance, low power and analog/mixed signal applications. Up to 8 levels of copper interconnect with the industry's first true low-k dielectric (SiLK, k=2.7) (Goldblatt et al., 2000) result in superior interconnect performance at aggressive pitches. A 2.28 /spl mu/m/sup 2/ SRAM cell is manufactured with high yield by introducing elongated local interconnects on the contact level without increasing process complexity. Trench based embedded DRAM is offered for large area memory. Modular analog devices as well as passive components like resistors, MIM capacitors and intrinsic inductors are integrated.

Keywords

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