The Limitations to Delay-Insensitivity in Asynchronous Circuits

Abstract
Asynchronous techniques that is, techniques that do not use clocks to implement sequencing are currently attracting considerable interest for digital VLSI circuit design particularly when the circuits produced are delay-insensitive (DI). A digital circuit is DI when its correct operation is independent of the delays in operators and in the wires connecting the operators, except that the delays are finite and positive. In this paper, we characterize the class of circuits that are entirely DI, and we show that this class is surprisingly limited: Practically all circuits of interest fall outside the class since closed circuits inside the class may contain only C-elements as multiple-input operators. The paper is organized as follows: First, we introduce the stable gate model of DI circuits, which is based on the notion of production rules (PRs) as elementary computation steps. We then define a partial ordering on transitions in the circuits. We prove that all DI circuits have to fulfill the so-called Unique-Successor-Set criterion; and we show that the class of circuits that meet this criterion is very limited. We also give a characterization of the class of computations that admit a DI implementation. Finally, we discuss what we consider to be the weakest compromise to delay-insensitivity, namely, isochronic forks.

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