High-speed, address-encoding arbiter architecture
- 2 February 2006
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 42 (3) , 170-171
- https://doi.org/10.1049/el:20063914
Abstract
An address-encoding arbiter architecture is presented that is suitable for large asynchronous circuits requiring address event representation readout. It provides improvement in power and speed, while also reducing area. By encoding the address in each layer of the arbiter tree, the address line loads are distributed throughout the tree, thus reducing the maximum single load on a line driver.Keywords
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