On-chip voltage noise monitor for measuring voltage bounce in power supply lines using a digital tester
- 7 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
With increasing interconnect densities, voltage bounce noise in power supply lines is becoming an important problem. In this paper, we describe a method to measure voltage bounce in a power supply line on a chip. We use a voltage comparator circuit to make the output a digital value. We connect this circuit in series to output the results with less pins.Keywords
This publication has 4 references indexed in Scilit:
- Design methodologies for noise in digital integrated circuitsPublished by Association for Computing Machinery (ACM) ,1998
- Power supply noise analysis methodology for deep-submicron VLSI chip designPublished by Association for Computing Machinery (ACM) ,1997
- Future directions in microprocessor technologyIEEE Journal of Solid-State Circuits, 1995
- FASTHENRY: a multipole-accelerated 3-D inductance extraction programIEEE Transactions on Microwave Theory and Techniques, 1994