Advanced self-alignment process technique with very thick sidewall for high speed GaAs LSIs

This publication has 2 references indexed in Scilit:

• An ultra-high speed GaAs DCFL flip-flop-MCFF (memory cell type flip flop)
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Buried p-layer SAINT for very high-speed GaAs LSI's with submicrometer gate length
  IEEE Transactions on Electron Devices, 1985