A Combined Force and Cut Algorithm for Hierarchical VLSI Layout
- 1 January 1982
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 671-677
- https://doi.org/10.1109/dac.1982.1585568
Abstract
No abstract availableThis publication has 5 references indexed in Scilit:
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- A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph RepresentationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- A proper model for the partitioning of electrical circuitsPublished by Association for Computing Machinery (ACM) ,1972
- An Efficient Heuristic Procedure for Partitioning GraphsBell System Technical Journal, 1970