A single chip NMOS ethernet controller

1 January 1983

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXVI, 70-71
https://doi.org/10.1109/isscc.1983.1156428

Abstract

The design of an integrated NMOS controller for a 10Mb Ethernet will be described. In addition to handling protocol, redundancy checking and preamble, the chip includes a self-calibrating tapped delay line for clock and data extraction.

Keywords

MOS DEVICES
ETHERNET NETWORKS
DELAY LINES
CLOCKS
LOGIC
VOLTAGE-CONTROLLED OSCILLATORS
FREQUENCY
PHYSICAL LAYER
TRANSMITTERS
CYCLIC REDUNDANCY CHECK

This publication has 1 reference indexed in Scilit:

Charge-Pump Phase-Lock Loops
IEEE Transactions on Communications, 1980