Reconvergent fanout analysis and fault simulation complexity of combinational circuits
- 8 October 1987
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 23 (21) , 1131-1133
- https://doi.org/10.1049/el:19870789
Abstract
The detectability of reconvergent fanout stem faults in a combinational logic circuit can be determined by explicitly simulating the faults within limited regions of the circuit. These regions are defined, and an estimate of the fault simulation complexity of the circuit is obtained. Results are presented for ten benchmark circuits.Keywords
This publication has 1 reference indexed in Scilit:
- Critical Path Tracing - An Alternative to Fault SimulationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983