Transmission line modeling of substrate resistances and CMOS latchup

1 July 1986

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 33 (7) , 945-954
https://doi.org/10.1109/T-ED.1986.22600

Abstract

Substrate resistance in epitaxial-CMOS is more appropriately viewed as a lossy transmission line than as a lumped resistor or as a resistance ladder network. Lossy transmission lines can be used to model a variety of substrate resistance configurations, including the resistance necessary to quantitatively predict turn on of the lateral parasitic bipolar during latchup. Voltage and current distributions predicted by the transmission line model are in excellent agreement with two-dimensional numerical simulations. Parameter values for the model are easily related to vertical doping profiles and to a wide variety of parasitic p-n-p-n layouts. For CMOS design the lateral bipolar's bypass resistor, commonly found in lumped element models of the parasitic p-n-p-n, is replaced by a transfer resistance derived from the transmission line model. Butted substrate contacts are shown to provide a worst-case design situation.

Keywords

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