Adder-based digital signal processor architecture for 80 NS cycle time
- 24 March 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 9, 692-695
- https://doi.org/10.1109/icassp.1984.1172308
Abstract
Architecture and performance tests of a digital signal processor with the following specific features are presented: Short cycle time of 80 ns, shift & add 2's complement arithmetic with saturation and sign-magnitude truncation operations, distributed memories with sophisticated address arithmetics, three stage pipelining, 16 bit instruction format, 20 bit internal data wordlength. In addition to standard problems sophisticated signal processing algorithms (wave digital filtering, Bergland's real-valued FFT, etc.) can powerfully be exploited. Furthermore, this concept is well-suited for implementing multiprocessor configurations.Keywords
This publication has 5 references indexed in Scilit:
- LSI signal processor architecture for telecommunications applicationsIEEE Transactions on Acoustics, Speech, and Signal Processing, 1982
- Transmultiplexers with Either Analog Conversion Circuits, Wave Digital Filters, or SC Filters - A ReviewIEEE Transactions on Communications, 1982
- A microcomputer with digital signal processing capabilityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- A single-chip digital signal processor for telecommunication applicationsIEEE Journal of Solid-State Circuits, 1981
- Numerical Analysis: A fast fourier transform algorithm for real-valued seriesCommunications of the ACM, 1968