An efficient multilevel placement technique using hierarchical partitioning
- 1 June 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 39 (6) , 432-439
- https://doi.org/10.1109/81.153634
Abstract
No abstract availableKeywords
This publication has 11 references indexed in Scilit:
- Clustering based simulated annealing for standard cell placementPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Timing driven placement using complete path delaysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An improved two-way partitioning algorithm with stable performance (VLSI)IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- Module placement for large chips based on sparse linear equationsInternational Journal of Circuit Theory and Applications, 1988
- Standard cell placement using simulated sinteringPublished by Association for Computing Machinery (ACM) ,1987
- Module Placement Based on Resistive Network OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1984
- Optimization by Simulated AnnealingScience, 1983
- A Linear-Time Heuristic for Improving Network PartitionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- Placement and average interconnection lengths of computer logicIEEE Transactions on Circuits and Systems, 1979
- An Efficient Heuristic Procedure for Partitioning GraphsBell System Technical Journal, 1970