Channel ion implantation for small-geometry high-performance CMOS-SOS circuits
- 1 March 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 33 (3) , 335-344
- https://doi.org/10.1109/t-ed.1986.22492
Abstract
This paper describes an experimental study of channel ion implantation for optimization of small-geometry (1-1.5 µm) n- and p-channel silicon-on-sapphire (SOS) MOSFET's for high-performance CMOS applications. The influence of a wide range of channel implantation conditions on device characteristics are reported, and optimum channel doping profiles identified. Adequate performance of NMOS devices is achieved by the use of double boron channel implants, but excellent PMOS devices are obtained by the use of very lightly doped near-intrinsic device islands.Keywords
This publication has 0 references indexed in Scilit: