The VLSI implementation of a square root algorithm

1 June 1985

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 159-165
https://doi.org/10.1109/arith.1985.6158929

Abstract

VLSI implementation of a square root algorithm is studied. Two possible implementations of the basic non-restoring algorithm are presented — the second is more area-efficient and modular than the first. The implementations are simple and easy to control, but, at the same time, are more area-time efficient than many existing designs. A hardware algorithm suited to microprogram implementation is also given. Extension of the algorithms to achieve ½ bit precision is discussed.

Keywords

REGISTERS
ALGORITHM DESIGN AND ANALYSIS
ADDERS
FLIP-FLOPS
HARDWARE
VERY LARGE SCALE INTEGRATION
CLOCKS

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