A new technique for standby leakage reduction in high-performance circuits

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27 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 40-41
https://doi.org/10.1109/vlsic.1998.687996

Abstract

A new standby leakage control technique, which exploits the leakage reduction offered by transistor stacks with "more than one 'off' device", demonstrates 2/spl times/ reduction in standby leakage power for a 32-bit static CMOS adder in a low-Vt, sub-1V, 0.1 /spl mu/m technology. Leakage reduction is achieved with minimal overheads in area, power and process technology. The dynamics of leakage reduction due to transistor stacks, and its influence on the overall leakage power of large circuits are elucidated for the first time.

Keywords

CMOS TECHNOLOGY
MOS DEVICES
LEAKAGE CURRENT
ADDERS
CMOS LOGIC CIRCUITS
SUBTHRESHOLD CURRENT
LOGIC GATES
LOGIC DEVICES
VOLTAGE
CAPACITANCE

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