New bounds for parallel prefix circuits
- 1 January 1983
- conference paper
- Published by Association for Computing Machinery (ACM)
- p. 100-109
- https://doi.org/10.1145/800061.808738
Abstract
In this paper, new upper and lower bounds are obtained for the number of gates in parallel prefix circuits with minimum depth when the number of inputs is a power of two. In addition, structural information concerning these circuits is described. Parallel prefix circuits with bounds imposed on the fan-out of the gates are also considered. In both cases, the upper and lower bounds obtained differ by small constant factors.Keywords
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