On the design and implementation of FIR and IIR digital filters with variable frequency characteristics
Open Access
- 1 November 2002
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
- Vol. 49 (11) , 689-703
- https://doi.org/10.1109/tcsii.2002.807574
Abstract
This paper studies the design and implementation of finite-impulse response (FIR) and infinite-impulse response (IIR) variable digital filters (VDFs), whose frequency characteristics can be controlled continuously by some control or tuning parameters. A least squares (LS) approach is proposed for the design of FIR VDFs by expressing the impulse response of the filter as a linear combination of basis functions. It is shown that the optimal LS solution can be obtained by solving a system of linear equations. By choosing the basis functions as piecewise polynomials, VDFs with larger tuning range than that of ordinary polynomial based approach results. The proposed VDF can be efficiently implemented using the familiar Farrow structure. Making use of the FIR VDF so obtained, an Eigensystem Realization Algorithm (ERA)-based model reduction technique is proposed to approximate the FIR VDF by a stable IIR VDF with lower system order. The advantages of the model reduction approach are: 1) it is computational simple which only requires the computation of the singular value decomposition of a Hankel matrix; 2) the IIR VDF obtained is guaranteed to be stable; and 3) the frequency response such as the phase response of the FIR prototype is well preserved. Apart from the above advantages, the proposed IIR VDF does not suffer from undesirable transient response during parameter tuning found in other approaches based on direct tuning of filter parameters. For frequency selective VDFs, about 40% of the multiplications can be saved using the IIR VDFs. The implementation of the proposed FIR VDF using sum-of-powers-of-two (SOPOT) coefficient and the multiplier block (MB) technique are also studied. Results show that about two-third of the additions in implementing the multiplication of the SOPOT coefficients can be saved using the multiplier block, which leads to significant savings in hardware complexity.Keywords
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