Clean formal semantics for VHDL

17 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 641-647
https://doi.org/10.1109/edtc.1994.326810

Abstract

A simple formal semantics for the standard hardware description language VHDL is set out in functional style. The presentation comprises an executable specification for a synchronously clocked VHDL simulator.

Keywords

CLOCKS
SIGNAL PROCESSING
WIRES
HARDWARE DESIGN LANGUAGES
STANDARDS DEVELOPMENT
NATURAL LANGUAGES
HUMANS
FUNCTIONAL PROGRAMMING
LIBRARIES
KERNEL

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