Ordered binary decision diagrams and circuit structure
- 7 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 13 references indexed in Scilit:
- Logic verification using binary decision diagrams in a logic synthesis environmentPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Evaluation and improvement of Boolean comparison method based on binary decision diagramsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Verification algorithms for VLSI synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Graph-Based Algorithms for Boolean Function ManipulationIEEE Transactions on Computers, 1986
- A new method for verifying sequential circuitsPublished by Association for Computing Machinery (ACM) ,1986
- Bandwidth and pebblingComputing, 1983
- NORA: a racefree dynamic CMOS technique for pipelined logic structuresIEEE Journal of Solid-State Circuits, 1983
- Pebble games for studying storage sharingTheoretical Computer Science, 1982
- The Generation of Optimal Code for Arithmetic ExpressionsJournal of the ACM, 1970
- Representation of Switching Circuits by Binary-Decision ProgramsBell System Technical Journal, 1959