Fabrication and characterization of a quarter micron gate CMOS using ultra-thin Si film (30 nm) on SIMOX substrate
- 7 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 2 references indexed in Scilit:
- Modeling of 0.1-µm MOSFET on SOI structure using Monte Carlo simulation techniqueIEEE Transactions on Electron Devices, 1986
- High-speed, low-power, implanted-buried-oxide CMOS circuitsIEEE Electron Device Letters, 1986