0.65 V device design with high-performance and high-density 100 nm CMOS technology for low operation power application

25 June 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 122-123
https://doi.org/10.1109/vlsit.2002.1015417

Abstract

A low-power, high-speed and high-density 100 nm CMOS technology is developed for very-low-voltage (Vds=0.65 V) operation by using ArF 193 nm lithography, high-performance transistors with sidewall notch, high-density SRAM cell (1.16 /spl mu/m/sup 2/) and copper (Cu) and very-low-k (VLK) interconnect (k/sub eff/=3). For reduction of power consumption and improvement of circuit speed in dynamic operation, high-current transistors at low voltage, interconnect with VLK dielectrics and transistors with reduced parasitic capacitance are required. High-performance transistors with sidewall notch to reduce overlap and junction capacitance and Cu/VLK interconnect with low-k SiC barriers realize higher circuit speed by 10% and lower power consumption by 80%, compared to 130 nm CMOS technology.

Keywords

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