Design of Asynchronous Unit Delays
- 1 October 1970
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-19 (10) , 896-902
- https://doi.org/10.1109/t-c.1970.222796
Abstract
An asynchronous unit delay is an n-input n-output asynchronous sequential circuit such that the present value of the output n-tuple is equal to the value of the input n-tuple prior to the last input change. The delay is of significance as a building block for shift register realizations of asynchronous circuits.Keywords
This publication has 4 references indexed in Scilit:
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- Equivalent Sequential CircuitsIRE Transactions on Circuit Theory, 1959
- Hazards and Delays in Asynchronous Sequential Switching CircuitsIRE Transactions on Circuit Theory, 1959
- The synthesis of sequential switching circuitsJournal of the Franklin Institute, 1954