1:4 demultiplexer architecture for Gbit/s lightwave systems

25 April 1991

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 27 (9) , 753-755
https://doi.org/10.1049/el:19910468

Abstract

A high speed 1:4 demultiplexer IC architecture featuring output bit alignment, reduced gate count, and improved timing over a conventional tree-type architecture demultiplexer is presented. Simulation results at 20 Gbit/s are obtained using an HBT process. The architecture can be directly extended to higher order demultiplexers, and is applicable to other processes supporting current-mode logic.

Keywords

1:4 DEMULTIPLEXER
IMPROVED TIMING
HBT PROCESS
DEMULTIPLEXER ARCHITECTURE
20 GBIT/S
IC ARCHITECTURE
LIGHTWAVE SYSTEMS
OUTPUT BIT ALIGNMENT
SIMULATION RESULTS
REDUCED GATE COUNT
CURRENT-MODE LOGIC

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