Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture

1 December 2004

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 421-424
https://doi.org/10.1109/fpt.2004.1393315

Abstract

This work evaluates an algorithm that maps a number of communicating processes to a heterogeneous tiled system on chip (SoC) architecture at run-time. The mapping algorithm minimizes the total amount of energy consumption, while still providing an adequate quality of service (QoS). A realistic example is mapped using this algorithm.

Keywords

RUNTIME
SYSTEM-ON-A-CHIP
TILES
COMPUTER ARCHITECTURE
ENERGY EFFICIENCY
ENERGY CONSUMPTION
NETWORK-ON-A-CHIP
APPLICATION SOFTWARE
MATHEMATICS
COMPUTER SCIENCE

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